1. Field of the Invention
The present invention generally relates to the manufacture of semiconductor devices, and more particularly, the present invention relates to the planarization of the surface of an insulation layer by chemical mechanical polishing (CMP) using a ceria-based slurry.
2. Description of the Related Art
As the degree of integration of microelectronic devices continues to increase, planarization processes used in the fabrication of such devices become more and more critical. That is, efforts to achieve highly integrated semiconductor devices are typically attended by the stacking of multiple interconnection and other layers on a semiconductor wafer. The resultant unevenness of the wafer surface presents a variety of problems which are well-documented in the art. Planarization processes are thus adopted at various stages of fabrication in an effort to minimize irregularities in the wafer surface.
One such planarization technique is chemical/mechanical polishing (CMP). In CMP, the wafer surface is pressed against a polishing pad in relative rotation. During polishing, an abrasive and chemically reactive solution known as a CMP slurry is made to flow into the polishing pad. This CMP technique planarizes the wafer surface by means of chemical and physical reactions, that is, by supplying the chemically reactive slurry as a thin film on a patterned surface of the wafer while at the same time physically pressing the relative rotating surface of the polishing pad against the surface of the wafer.
One common application of CMP is in shallow trench isolation (STI). In STI techniques, relatively shallow isolation trenches are formed which function as field regions used to separate active regions on a wafer. In this process, a nitride (SiN) stop layer is deposited over on a semiconductor substrate. The nitride stop layer is then patterned and etched to form trenches which extend through the nitride stop layer and into the semiconductor substrate. Thereafter, an insulating oxide layer (which will ultimately forms the trench oxide regions) is deposited so as to fill the trenches and cover the surface of the nitride stop layer. The oxide layer is then subjected to CMP so as to remove the oxide layer down to the level of the nitride stop layer. In particular, during the CMP process, the oxide layer is removed until the upper surface of the nitride stop layer is exposed. Due to differing chemical and physical characteristics thereof, the oxide and nitride layers exhibit different removal rates when subjected to CMP using known slurries. The ratio of these removal rates at least partially defines the xe2x80x9cselectivityxe2x80x9d of the slurry being used. The lower the selectivity of the slurry, the more nitride that will be polished away during the CMP process.
Recently, ceria-based slurries (hereinafter, referred to as xe2x80x9cceria slurriesxe2x80x9d) have been introduced which contain cerium oxide particles and which provide suitable abrasive characteristics for insulation layers containing SiO2 as a major component. These ceria slurries have a relatively high oxide-to-nitride selectivity of about 45:1. In contrast, commonly used silica-based slurries (hereinafter, referred to as xe2x80x9csilica slurriesxe2x80x9d) have oxide-to-nitride selectivities of about 4:1. As such, the stopper function of the nitride stop layer is more effective using ceria slurries. Further, variations in the thickness of the nitride layer after CMP processing are minimized.
One drawback of ceria slurries, however, resides in fact that the oxide removal rate thereof drops sharply in the case where the oxide surface being polished is uneven and/or contains pattern steps. In contrast, the oxide removal rate of silica slurries is not dependent on whether the oxide surface being polished is uneven and/or contains pattern steps.
Two examples in which the oxide surface being polished is uneven or contains pattern steps are described below with reference to FIG. 1 and FIG. 2, which are sectional views for use in explaining conventional trench refill processes in the manufacture of semiconductor devices at a comparatively small design rule.
In FIG. 1, a nitride pattern 12 having a predetermined surface configuration is formed over a semiconductor substrate 10. Exposed portions of the semiconductor substrate 10 are then etched to a predetermined depth to form a plurality of trenches. These trenches are then filled with a material which is highly flowable and thus exhibits a favorable filling property, such as a high density plasma oxide (HDP) material, thereby resulting in a first oxide layer 22. The favorable filling property of the material ensures sufficient step coverage (without voids) even for trenches having high aspect ratios which are typically resident in a cell array region. Further, as shown in FIG. 1, the HDP material is also deposited on the nitride layer 12 between the trenches. These portions of the first oxide layer 22 are shown in FIG. 1 as having triangular cross-sections. Then, a conformable material which forms a second oxide layer 24 is deposited to a uniform thickness over the first oxide layer 22. Examples of the material of the second oxide layer 24 include borophosphosilicate glass (BPSG), undoped silicate glass (USG), and plasma-enhanced tetraethylorthosilicate (TEOS). The cross-sectional profile of the first oxide layer 22 is reflected in the surface configuration of the second oxide layer 24. That is, as shown in FIG. 1, local steps A are formed in the surface of the second oxide layer 24. In addition, local steps B are formed between the cell array region having relatively narrow trenches and a peripheral circuit region having relatively wide trenches.
The configuration of FIG. 2 differs from that of FIG. 1 in that a single oxide layer 24 is deposited in the configuration of FIG. 2 (i.e., the deposition of a highly flowable layer 22 of FIG. 1 is omitted). As shown, even in the absence of the initial deposition of the layer 22, the underlying trenches of the cell array region create local steps C in the surface of the second oxide layer 24 (e.g., USG layer). Also, as shown, local steps similar to the steps B of FIG. 1 are formed between the cell array region having relatively narrow trenches and a peripheral circuit region having relatively wide trenches.
FIG. 3 is a graph which comparatively shows CMP performances of silica and ceria slurries in the polishing of the stepped-surface cell array region to reduce or eliminate the local steps B shown in FIG. 1. The results of FIG. 3 were measured with respect to a semiconductor substrate 10 in which an HDP first oxide layer 22 and a PE-TEOS second oxide layer 24 were deposited in sequence. In FIG. 3, the plot xe2x80x9caxe2x80x9d for silica slurry shows an oxide removal rate of about 3000 xc3x85/min in the cell array region. The same result is observed when the CMP is applied under the same conditions to an oxide layer which does not have a stepped surface. In contrast, the plot xe2x80x9cbxe2x80x9d for ceria slurry shows an oxide removal rate of about 160 xc3x85/min in the cell array region. This oxide removal rate is very low when compared to the CMP performance of ceria slurry (about 3300 xc3x85/min, not shown) when applied to a oxide layer which does not have surface steps. The sharp degradation of the oxide removal rate of the ceria slurry tends to occur where the oxide layer surface of the cell array region contains steps as shown in FIG. 1 and FIG. 2.
For these reasons, the conventional CMP process is carried out in two stages. In a first stage, the silica slurry is first utilized to polish the oxide layer since is has a high removal rate that is not degraded by the presence of steps in the oxide surface. Then, in a second stage, the ceria slurry is utilized to again polish the oxide layer since it exhibits a high oxide-to-nitride selectivity and thus enhances the stopper function of the nitride pattern. This need for two different process stages using two different slurries increases the overall complexity of the CMP process, thus increasing costs and lowering throughput.
It is an object of the present invention to provide an effective method for planarizing an oxide layer having local steps in a surface using a single stage chemical mechanical polishing (CMP) process.
To achieve the object of the present invention, there is provided a planarization method for a semiconductor device which a nitride pattern is formed over a semiconductor substrate, and an oxide layer is then formed over the semiconductor substrate and the nitride pattern. Next, a sacrificial insulation layer which is devoid of surface steps is formed over the oxide layer. The sacrificial insulation layer and the oxide layer are then polished by CMP using the ceria-based slurry and using the nitride pattern as a stopper.
The planarization method is effective to compensate a degradation in ceria slurry performance which would otherwise result from the presence of steps in the surface of the oxide layer. Such steps generally occur in cases where the oxide layer is used to fill trenches formed in an active region of the semiconductor substrate.